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Latch-up in Integrated Circuits under Single and Periodic Electrical Overstress

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dc.contributor.authorShemonaev, A.
dc.contributor.authorAnikin, A.
dc.contributor.authorEpifantsev, K.
dc.contributor.authorSkorobogatov, P.
dc.contributor.authorШемонаев, Александр Николаевич
dc.contributor.authorАникин, Андрей Александрович
dc.contributor.authorЕпифанцев, Константин Алексеевич
dc.contributor.authorСкоробогатов, Петр Константинович
dc.date.accessioned2024-12-25T15:57:36Z
dc.date.available2024-12-25T15:57:36Z
dc.date.issued2022
dc.description.abstract© 2022 IEEE.This paper describes the results of sensitivity test to latch-up of several types of ICs (SRAM, EEPROM memory, ADC, microcontroller) caused by single and multiple electrical overstresses. It was shown, that electrical strike with a high-repetition rate increases the sensitivity and vulnerability of ICs to latch-up. The article describes some aspects of the test procedure, which may affect on IC's sensitivity results.
dc.identifier.citationLatch-up in Integrated Circuits under Single and Periodic Electrical Overstress / Shemonaev, A. [et al.] // Moscow Workshop on Electronic and Networking Technologies, MWENT 2022 - Proceedings. - 2022. - 10.1109/MWENT55238.2022.9802266
dc.identifier.doi10.1109/MWENT55238.2022.9802266
dc.identifier.urihttps://www.doi.org/10.1109/MWENT55238.2022.9802266
dc.identifier.urihttps://www.scopus.com/record/display.uri?eid=2-s2.0-85134038775&origin=resultslist
dc.identifier.urihttps://openrepository.mephi.ru/handle/123456789/28128
dc.relation.ispartofMoscow Workshop on Electronic and Networking Technologies, MWENT 2022 - Proceedings
dc.titleLatch-up in Integrated Circuits under Single and Periodic Electrical Overstress
dc.typeConference Paper
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