Персона: Аткин, Эдуард Викторович
Email Address
Birth Date
Результаты поиска
Differential Input Area Efficient Current Comparator
© 2019 IEEE.Differential input area efficient current comparator for multichannel detector (sensor) applications is presented. Comparator consists of current preamplifier, hysteresis latch, amplifier-voltage limiter and output low-voltage to CMOS translator, having built-in polarity selection switch. The latch geometry was chosen to feature non-zero hysteresis and minimum size. The key features of the proposed solution are low voltage swing before translator, low power consumption and simplicity. The comparator was developed in UMC 180 nm MMRF CMOS process. The power consumption is in range of 60\ \mu \mathrm{W} at 1.8 V for all PVT variations. Its layout cell was designed to be an area efficient one and occupies 1200\ \mu \mathrm{m} {2}.
Design and analysis of 2.56 Gbps CML CMOS transceiver with specific load for physical instrumentation applications
Read-out analog channel with interpolator for signal peak finding
© Published under licence by IOP Publishing Ltd.A prototype of an analog channel with a digital processing system for reading signals from GEM detectors is presented. Each channel consists of a charge-sensitive amplifier, a shaper, a switch, an amplifier and a 10-bits ADC. The data from the ADC is processed by the digital system based on an interpolator to find signal peaks. The interpolator uses a 6th order Lagrange polynomial. It maintains peak detection accuracy within 1.1 LSB at 25 MHz ADC sampling rate and 270 ns shaper peaking time.
Differential input area efficient current comparator
© 2019 Author(s).Differential input area efficient current comparator for multichannel detector (sensor) applications is presented. Comparator consists of current preamplifier, hysteresis latch, amplifier-voltage limiter and output low-voltage to CMOS translator, having built-in polarity selection switch. The latch geometry was chosen to feature non-zero hysteresis and minimum size. The key features of the proposed solution are low voltage swing before translator, low power consumption and simplicity. The comparator was developed in UMC 180 nm MMRF CMOS process. It consumes less than 60 μW at 1.8 V. Its layout cell was designed as an area efficient one and occupies 1200 μm2.
Implementation of the deconvolution method for signal peak detection in read-out ASIC
© Published under licence by IOP Publishing Ltd.An application of the deconvolution method for signal peak detection in read-out ASIC for GEM detectors is described. Instead of usage of the conventional analog or digital peak detector, deconvolution technique to define the signal maximum was studied. In this case the digital data coming from the ADC are processed by a digital filter that deconvolves according to the pre-determined transfer function of the analog channel. Such processing allows to identify the signal peak values and also to provide reasonable pileup rejection. That enables higher rates of the incoming signals and reduces the amount of lost data. Combined with the analog channel employing 10-bit 25 MHz sampling rate ADC and 250 ns time constant 2nd-order shaper, the designed deconvolution block maintains peak detection accuracy within 9 LSBs. Time resolution of peak separation is 4 ADC sampling intervals or 100 ns.
Development of Data Concentration Method and Its Implementation in a Radiation-Tolerant CMOS Application Specific Integrated Circuit
© 2021, Pleiades Publishing, Ltd.Abstract: The results of the concentration method development for the data coming from the detector integrated circuits, intended for the experimental facilities MPD and BM@N, are presented. Charged particle detectors at these installations are characterized by a high granularity and accuracy of the detecting equipment. That results in a large data volume and the need to transfer processed data at a gigabit rate. Therefore, ASIC of the data concentrator requires both a high integration and use of specific structure as well as circuit and layout to provide an increased radiation tolerance. A specific feature of the ASIC is its ability to operate in the actual radiation background of the experiments estimated by up to 100 kRad in terms of immunity to heavy charged particles. In order to approbate the method and solutions on improvement of the radiation tolerance, the design results of a prototype 65 nm CMOS ASIC for read-out the signals from two SAMPA front-end chips cards are described. ASIC is intended for data receipt, concentration and subsequent transmission at a rate of 2.56 Gbit/s over micro-coaxial cables of 1 m length.
Prototype Data Concentrator ASIC for Time-Projection Chamber of MPD Experiment
© 2022, Pleiades Publishing, Ltd.Abstract: The results of the prototype development of a data concentrator application-specific integrated circuit (ASIC) for the time-projection chamber of the MPD experiment (NICA, Dubna) are presented. ASIC is designed to serialize data coming from two SAMPA detector chips and transmit them via AWG 36 type electrical cables of up to 1 m length at 2.56 Gbit/s transmission rate to the data acquisition controller board. The article describes the structure, main characteristics and layout of the ASIC, as well as the protocol of data exchange with the external controller. A description is given of the design methods used to ensure the radiation tolerance of ASIC to the effects of high-energy particles. The prototypes are manufactured using 65 nm CMOS process from TSMC and embedded in CPGA120 package. The total power consumption of the ASIC does not exceed 500 mW.
Parametric layout cell design of N-MOS transistor with enhanced radiation hardened properties
© 2020 American Institute of Physics Inc.. All rights reserved.NMOS design methodology with increased radiation hardness based on the standard manufacturer's technological libraries is presented. Key model parameters definition are discussed, as well as layout design for parametrized components and connected with layout configuration features when projecting integral layout. Test structures are presented for components characterization in radiation environment.