The Price of Routing in FPGAs

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dc.creatorDe Dinechin,Florent
dc.date2000
dc.date.accessioned2024-02-06T12:50:30Z
dc.date.available2024-02-06T12:50:30Z
dc.descriptionStudying the architectural evolution of mainstream field programmable gate arrays (FPGAs) leads to the following remark: in these circuits, the proportion of silicon devoted to reconfigurable routing is increasing, reducing the proportion of silicon available for computation resources. A quantitative analysis shows that this trend, if pursued, will lead to a widening gap between FPGA performance and VLSI performance. Some prospective solutions to this problem are discussed.
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dc.identifierhttps://doi.org/10.3217/jucs-006-02-0227
dc.identifierhttps://lib.jucs.org/article/27655/
dc.identifier.urihttps://openrepository.mephi.ru/handle/123456789/7714
dc.languageen
dc.publisherJournal of Universal Computer Science
dc.relationinfo:eu-repo/semantics/altIdentifier/eissn/0948-6968
dc.relationinfo:eu-repo/semantics/altIdentifier/pissn/0948-695X
dc.rightsinfo:eu-repo/semantics/openAccess
dc.rightsJ.UCS License
dc.sourceJUCS - Journal of Universal Computer Science 6(2): 227-239
dc.subjectFPGA
dc.subjectreconfigurable computing
dc.subjectrouting resources
dc.subjecthardware complexity
dc.titleThe Price of Routing in FPGAs
dc.typeResearch Article
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