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Differential Input Area Efficient Current Comparator

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dc.contributor.authorSerazetdinov, A. R.
dc.contributor.authorAtkin, E. V.
dc.contributor.authorСеразетдинов, Артур Рафикович
dc.contributor.authorАткин, Эдуард Викторович
dc.date.accessioned2024-11-21T14:53:29Z
dc.date.available2024-11-21T14:53:29Z
dc.date.issued2019
dc.description.abstract© 2019 IEEE.Differential input area efficient current comparator for multichannel detector (sensor) applications is presented. Comparator consists of current preamplifier, hysteresis latch, amplifier-voltage limiter and output low-voltage to CMOS translator, having built-in polarity selection switch. The latch geometry was chosen to feature non-zero hysteresis and minimum size. The key features of the proposed solution are low voltage swing before translator, low power consumption and simplicity. The comparator was developed in UMC 180 nm MMRF CMOS process. The power consumption is in range of 60\ \mu \mathrm{W} at 1.8 V for all PVT variations. Its layout cell was designed to be an area efficient one and occupies 1200\ \mu \mathrm{m} {2}.
dc.format.extentС. 305-308
dc.identifier.citationSerazetdinov, A. R. Differential Input Area Efficient Current Comparator / Serazetdinov, A.R., Atkin, E.V. // 2019 IEEE 31st International Conference on Microelectronics, MIEL 2019 - Proceedings. - 2019. - P. 305-308. - 10.1109/MIEL.2019.8889641
dc.identifier.doi10.1109/MIEL.2019.8889641
dc.identifier.urihttps://www.doi.org/10.1109/MIEL.2019.8889641
dc.identifier.urihttps://www.scopus.com/record/display.uri?eid=2-s2.0-85075361760&origin=resultslist
dc.identifier.urihttps://openrepository.mephi.ru/handle/123456789/18905
dc.relation.ispartof2019 IEEE 31st International Conference on Microelectronics, MIEL 2019 - Proceedings
dc.titleDifferential Input Area Efficient Current Comparator
dc.typeConference Paper
dspace.entity.typePublication
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