Персона: Аткин, Эдуард Викторович
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Differential Input Area Efficient Current Comparator
© 2019 IEEE.Differential input area efficient current comparator for multichannel detector (sensor) applications is presented. Comparator consists of current preamplifier, hysteresis latch, amplifier-voltage limiter and output low-voltage to CMOS translator, having built-in polarity selection switch. The latch geometry was chosen to feature non-zero hysteresis and minimum size. The key features of the proposed solution are low voltage swing before translator, low power consumption and simplicity. The comparator was developed in UMC 180 nm MMRF CMOS process. The power consumption is in range of 60\ \mu \mathrm{W} at 1.8 V for all PVT variations. Its layout cell was designed to be an area efficient one and occupies 1200\ \mu \mathrm{m} {2}.
Design and analysis of 2.56 Gbps CML CMOS transceiver with specific load for physical instrumentation applications
Energy Spectra of Cosmic-Ray Protons and Nuclei Measured in the NUCLEON Experiment Using a New Method
Some results of studies of cosmic rays obtained during the NUCLEON space experiment in 2015-2017 are presented. This experiment was intended for direct measurements of the energy spectra and chemical composition of cosmic rays (Z = 1-30) in the energy range 2-500 TeV. Results presented include energy spectra for various abundant nuclei measured using the new Kinematic Lightweight Energy Meter (KLEM). The primary energies are established using the spatial densities of secondary particles produced in inelastic interactions with a carbon target.
Parametric layout cell design of N-MOS transistor with enhanced radiation hardened properties
© 2020 American Institute of Physics Inc.. All rights reserved.NMOS design methodology with increased radiation hardness based on the standard manufacturer's technological libraries is presented. Key model parameters definition are discussed, as well as layout design for parametrized components and connected with layout configuration features when projecting integral layout. Test structures are presented for components characterization in radiation environment.
Differential input area efficient current comparator
© 2019 Author(s).Differential input area efficient current comparator for multichannel detector (sensor) applications is presented. Comparator consists of current preamplifier, hysteresis latch, amplifier-voltage limiter and output low-voltage to CMOS translator, having built-in polarity selection switch. The latch geometry was chosen to feature non-zero hysteresis and minimum size. The key features of the proposed solution are low voltage swing before translator, low power consumption and simplicity. The comparator was developed in UMC 180 nm MMRF CMOS process. It consumes less than 60 μW at 1.8 V. Its layout cell was designed as an area efficient one and occupies 1200 μm2.
Review of the Results from the NUCLEON Space Experiment
© 2019, Allerton Press, Inc.Abstract: The NUCLEON space observatory was developed to measure the spectra of cosmic ray nuclei with individual charge resolution in the energy range of several TeV to 1 PeV per particle. The NUCLEON was launched into a heliosynchronous orbit as an additional load on the Resurs-2P production satellite on December 28, 2014, and it is still in operation (2019). This work is a brief review of the results from the NUCLEON observatory over three years of operation in orbit. The spectra of the main primary abundant nuclei and product nuclei of cosmic rays (CRs) are presented. Some new interesting features of the CR spectra found in the NUCLEON data are discussed.
Charge Sensitive Amplifier with Pseudo-differential Output
© 2021, Pleiades Publishing, Ltd.Abstract: The design results of a charge-sensitive amplifier (CSA) with a pseudo-differential output are presented. The CSA is intended for operation with signals of both polarities at the dynamic range up to 100 fC and parasitic detector capacitances up to 100 pF. In order to form a pseudo-differential signal, a first-order low-pass filter having a cutoff frequency of several hertz was used. CSA is designed in 180 nm CMOS process.
Implementation of Interpolation in Read-out ASIC for GEM Detectors
© 2021, Pleiades Publishing, Ltd.Abstract: The results of designing a readout ASIC for GEM detectors are presented. The chip has a built-in digital signal processing system intended to calculate the maximum signal amplitude (input charge) and based on the principle of interpolation. Using interpolation allowed to calculate the maximum charge amplitude with an accuracy of 1.5 LSB at using a built-in 10-bit ADC having a maximum conversion frequency of 25 MHz and a shaping amplifier with a peaking time of 320 ns. The readout ASIC was designed in UMC MMRF 180 nm CMOS process.
Prototype Data Concentrator ASIC for Time-Projection Chamber of MPD Experiment
© 2022, Pleiades Publishing, Ltd.Abstract: The results of the prototype development of a data concentrator application-specific integrated circuit (ASIC) for the time-projection chamber of the MPD experiment (NICA, Dubna) are presented. ASIC is designed to serialize data coming from two SAMPA detector chips and transmit them via AWG 36 type electrical cables of up to 1 m length at 2.56 Gbit/s transmission rate to the data acquisition controller board. The article describes the structure, main characteristics and layout of the ASIC, as well as the protocol of data exchange with the external controller. A description is given of the design methods used to ensure the radiation tolerance of ASIC to the effects of high-energy particles. The prototypes are manufactured using 65 nm CMOS process from TSMC and embedded in CPGA120 package. The total power consumption of the ASIC does not exceed 500 mW.