The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation

Pérez,Oscar; Berviller,Yves; Tanougast,Camel; Weber,Serge

The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation

Авторы

Pérez,Oscar

Berviller,Yves

Tanougast,Camel

Weber,Serge

Издатель

Journal of Universal Computer Science

Описание

This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining and dynamic total reconfiguration (DTR). The originality of our implementation is that it computes sequentially in the FPGA the Key and Cipher part of the AES algorithm. This dynamic reconfiguration implementation allows a good optimization of logic resources with a high throughput. This architecture employs only 11619 slices allowing a considerable economy of the resources and reaching a maximum throughput of 44 Gbps.

Ключевые слова

AES , FPGA , dynamic total reconfiguration , reconfiguration controller , pipeline , registers , iterative looping , unrolling looping , throughput , latency , reconfiguration time