Publication: Masking of SET in a CMOS Triple Majority Gate on Logic NAND under Impacts of Single Ionizing Particles
Дата
2021
Авторы
Katunin, Y. V.
Stenin, V. Y.
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© 2021 IEEE.This work presents the 65-nm bulk CMOS Triple Majority Gate (TMG) with an original topological structure, in which the all transistors of the output 3NAND gate one by one are introduced into the corresponding groups of transistors of the three input 2NAND gates. A feature of the majority element is the masking of noise pulses that occurs when collecting charge from the track after switching the element from the inputs from '0' to '1' and before switching the element from '1' to '0'. The TCAD simulation ot SET uses the linear energy transfer 60 Me V.cm2/mg to tracks with the normal direction to the chip surface.
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Katunin, Y. V. Masking of SET in a CMOS Triple Majority Gate on Logic NAND under Impacts of Single Ionizing Particles / Katunin, Y.V., Stenin, V.Y. // Proceedings of the International Conference on Microelectronics, ICM. - 2021. - 2021-September. - P. 321-324. - 10.1109/MIEL52794.2021.9569059