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One approach to compact testing of digital circuits

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dc.contributor.authorBerezkin, E. F.
dc.contributor.authorБерезкин, Евгений Феофанович
dc.date.accessioned2024-11-21T08:14:41Z
dc.date.available2024-11-21T08:14:41Z
dc.date.issued2019
dc.description.abstract© 2019 Institut za Istrazivanja. All rights reserved. A problem of signature analyzer synthesis with required properties is solved for digital schemes compact testing. The main attention is devoted to the issues of eliminating losses of diagnostic information and to simplicity of structural organization. Solutions are based on detecting all error vectors or matrices resulting from failures of diagnostics objects related to the postulated class. Any other error vectors or matrices can be non-detectable and are excluded from consideration. For the compact testing of separate units of complex digital systems, the problem of synthesis of the generator structure that reproduces an assigned sequence of binary sets is being solved. Increased attention is given to issues of the non-excessive reproduction of sets sequence and structural organization simplicity. The solution is based on the application of a mathematical tool for linear sequence machines. A software implementation of the mathematical model is proposed. Error vectors or matrix detection process visualization aids are given. Additionally, means of the binary sets generation process visualization are presented.
dc.format.extentС. 26-34
dc.identifier.citationBerezkin, E. F. One approach to compact testing of digital circuits / Berezkin, E.F. // Journal of Applied Engineering Science. - 2019. - 17. - № 1. - P. 26-34. - 10.5937/jaes17-18539
dc.identifier.doi10.5937/jaes17-18539
dc.identifier.urihttps://www.doi.org/10.5937/jaes17-18539
dc.identifier.urihttps://www.scopus.com/record/display.uri?eid=2-s2.0-85065335526&origin=resultslist
dc.identifier.urihttps://openrepository.mephi.ru/handle/123456789/17903
dc.relation.ispartofJournal of Applied Engineering Science
dc.titleOne approach to compact testing of digital circuits
dc.typeArticle
dspace.entity.typePublication
oaire.citation.issue1
oaire.citation.volume17
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relation.isAuthorOfPublication.latestForDiscovery656d6c4d-9970-478e-aad8-8d644885666f
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