Publication: CMOS Majority Element Based on NAND Logic with Reduced Sensitivity to Single Ionizing Particles
Дата
2021
Авторы
Katunin, Y. V.
Stenin, V. Y.
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© 2021, Pleiades Publishing, Ltd.Abstract: The results of modeling the elements of a triple majority gate based on the CMOS NAND logic elements are presented. Modeling is carried out using the 3D TCAD of physical models of CMOS transistors according to the design standard of 65-nm bulk technology with the shallow trench isolation (STI) of transistor groups when the charge is collected by transistors from the tracks of single ionizing particles with linear energy transfer (LET) in the range from 10 to 90 MeV cm2/mg. The collection of a charge from the track leads to the formation of noise pulses. The majority gate is made on 18 transistors and has an original topological structure, in which the transistors of the 3NAND output logic element are inserted one-by-one into the corresponding groups of transistors of the three 2NAND input elements. This reduces the duration of the pulse noise at the output of the majority element with input signals A = B = C = 0 due to the joint collection of a charge from the particle track by transistors of series-connected 2-input NAND and 3-input NAND logic elements. A feature of the majority element is noise masking (blocking the transmission to the output of noise pulses that occur on its internal NAND nodes) when the signals at the inputs of the element are A = B = C = 1. With signals at the inputs of element A = B = C = 0, the duration of the noise pulses are in the range of 50 to 200 ps with the LET to the track of 60 to 90 MeV cm2/mg with the track input points into NMOS transistors; and 250–400 ps, with the track input points into PMOS transistors.
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Katunin, Y. V. CMOS Majority Element Based on NAND Logic with Reduced Sensitivity to Single Ionizing Particles / Katunin, Y.V., Stenin, V.Y. // Russian Microelectronics. - 2021. - 50. - № 6. - P. 394-403. - 10.1134/S1063739721050073