Publication: Two-Step Pipeline SAR ADC with passive Charge Sharing between Cascades
Дата
2019
Авторы
Osipov, D.
Gusev, A.
Paul, S.
Shumikhin, V.
Journal Title
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Volume Title
Издатель
Аннотация
© 2019 IEEE.A new pipeline SAR ADC architecture without gain between stages is proposed. This architecture can benefit the implementation of high speed SAR ADCs in two ways: first, as a two-stage pipeline, it increases the speed of conversion by a factor of two; second, because of the capacitive DAC split, it avoids the switching of large capacitors for most significant bits definition. The architecture was verified by the design of a 10-bit ADC with a maximum conversion speed of 37 MS/s. The ADC was designed and laid out using the 180 nm CMOS technology of UMC. The simulated ENOB is equal to 8.42 bits, and the power consumption at maximum sampling speed does not exceed 1.01 mW. Moreover, the Walden FoM of the proposed ADC is 79.7 fJ/conv.-step.
Описание
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Цитирование
Two-Step Pipeline SAR ADC with passive Charge Sharing between Cascades / Osipov, D. [et al.] // 2019 IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019 - Proceedings. - 2019. - 10.1109/NORCHIP.2019.8906898
URI
https://www.doi.org/10.1109/NORCHIP.2019.8906898
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https://www.scopus.com/record/display.uri?eid=2-s2.0-85075991520&origin=resultslist
http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcAuth=Alerting&SrcApp=Alerting&DestApp=WOS_CPL&DestLinkType=FullRecord&UT=WOS:000722212700002
https://openrepository.mephi.ru/handle/123456789/18990