Publication:
Impact Modeling of Single Ionizing Particles on the CMOS Triple Majority Gate

dc.contributor.authorKatunin, Y. V.
dc.contributor.authorStenin, V. Y.
dc.date.accessioned2024-11-26T12:50:01Z
dc.date.available2024-11-26T12:50:01Z
dc.date.issued2020
dc.description.abstract© 2020 IEEE.Results of modeling 65 nm CMOS the Triple Majority Gate on AND and OR logical elements for redundant systems are presented. The AND and OR elements contain inverters located before and after transistors of their NAND and NOR elements. This reduces the duration of the noise pulses when exposed to single ionizing particles. TCAD simulations use particle tracks passing along the normal to the chip crystal surface. With a linear energy transfer of 60 MeV-cm2/mg, the reduction in the pulse duration of noise at the output of CMOS AND (OR) gates is from 2 to 5 times.
dc.identifier.citationKatunin, Y. V. Impact Modeling of Single Ionizing Particles on the CMOS Triple Majority Gate / Katunin, Y.V., Stenin, V.Y. // Moscow Workshop on Electronic and Networking Technologies, MWENT 2020 - Proceedings. - 2020. - 10.1109/MWENT47943.2020.9067332
dc.identifier.doi10.1109/MWENT47943.2020.9067332
dc.identifier.urihttps://www.doi.org/10.1109/MWENT47943.2020.9067332
dc.identifier.urihttps://www.scopus.com/record/display.uri?eid=2-s2.0-85084003515&origin=resultslist
dc.identifier.urihttps://openrepository.mephi.ru/handle/123456789/21652
dc.relation.ispartofMoscow Workshop on Electronic and Networking Technologies, MWENT 2020 - Proceedings
dc.titleImpact Modeling of Single Ionizing Particles on the CMOS Triple Majority Gate
dc.typeConference Paper
dspace.entity.typePublication
relation.isOrgUnitOfPublication06e1796d-4f55-4057-8d7e-bb2f3b5676f5
relation.isOrgUnitOfPublication.latestForDiscovery06e1796d-4f55-4057-8d7e-bb2f3b5676f5
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